1. Field of the Invention
The invention relates to a digital-to-analog converter, more particularly to a digital-to-analog converter for converting an n-bit digital signal into a corresponding analog signal, controlled by a lower-order signal portion of the n-bit digital signal, and including a relatively small number of passive components such as resistors and switches.
2. Description of the Related Art
Digital-to-analog (D/A) converters are widely used in various integrated circuits, such as in a liquid crystal display driver circuit. As shown in FIG. 1, a conventional D/A converter 1 is adapted to convert an N-bit digital signal into a corresponding analog signal. The conventional D/A converter 1 includes a resistor string 10 including a plurality of resistors (101˜108), and a switch multiplexer 11 including a plurality of switches (N0˜N7). The resistor string 10 has first and second endmost nodes (n8), (n0), and a plurality of intermediate nodes (n1˜n7). Each of the switches (N0˜N7) is connected between an output node Vout and a respective one of the second endmost and intermediate nodes (n0˜n7). The switches (N0˜N7) are controlled to open or close in response to the N-bit digital signal (D2, D1, D0) inputted into the switch multiplexer 11 such that one of the switches (N0˜N7) is selected to connect a corresponding one of the second endmost and intermediate nodes (n0˜n7) to the output node Vout in accordance with the digital signal (D2, D1, D0).
With such a circuit architecture, 2N resistors and 2N switches are required, where N represents the bit resolution of the D/A converter. The conventional D/A converter 1 illustrated in FIG. 1 is a 3-bit D/A converter, and therefore eight (since 23=8) resistors (101˜108) and eight switches (N0˜N7) are required.
Operation of the conventional D/A converter 1 requires application of first and second reference voltage sources +Vref, −Vref to the first and second endmost nodes (n8) (n0) of the resistor string 10, respectively. The resistors (101˜108), having equal resistances (R), divide a voltage difference ΔV between the first and second endmost nodes (n8), (n0) into eight equally-sized voltage steps, where ΔV=+Vref−(−Vref)=2 Vref. Therefore, there is a voltage drop of
      1    8    ⁢  ΔVacross each of the resistors (101˜108). In particular, the voltage at the second endmost node (n0) is −Vref, and the voltages at the intermediate nodes (n1˜n7) are
      (                  -                  V          ref                    +                        1          8                ⁢        Δ        ⁢                                  ⁢        V              )    ,          ⁢      (                  -                  V          ref                    +                        2          8                ⁢        Δ        ⁢                                  ⁢        V              )    ,      …    ⁢                  ⁢          (                        -                      V            ref                          +                              7            8                    ⁢          Δ          ⁢                                          ⁢          V                    )        ,respectively. The digital signal (D2, D1, D0) controls the switches (N0˜N7) such that one of the switches (N0˜N7) is closed, while the others are opened, to tap the voltage at the respective one of the second endmost and intermediate nodes (n0˜n7) to the output node Vout.
For example, if the digital signal (D2, D1, D0) inputted into the switch multiplexer 11 is “101”, a decoder 12 of the switch multiplexer 11 decodes the digital signal (D2, D1, D0) as a hexadecimal “5” that controls the corresponding switch (N5) to close and the rest of the switches (N0˜N4, N6˜N7) to open such that the voltage
  (            -              V        ref              +                  5        8            ⁢      ΔV        )at the corresponding intermediate node (n5) is tapped to the output node Vout.
However, this circuit architecture is only suitable for low-bit resolution applications because of its large chip size, which is attributed to the large required number of resistors and switches that grow in exponential functions of base two, where the exponent is the bit resolution (N), i.e., 2N resistors and 2N switches are required for N-bit resolution.
Shown in FIG. 2 is another 3-bit conventional D/A converter 2 adapted to convert a 3-bit digital signal (D0, D1, D2) into a corresponding analog signal. The 3-bit conventional D/A converter 2 includes a resistor string 20 that includes eight resistors (201˜208), and a switch multiplexer 21 including a plurality of first, second and third switches (G0˜G7), (G8˜G11)., (G12˜Gl3). As in the previous conventional D/A converter 1, the resistor string 20 has first and second endmost nodes (n8), (n0), and a plurality of intermediate nodes (n1˜n7). Each of the first switches (G0˜G7) is connected to a respective one of the second endmost and intermediate nodes (n0˜n7), and is operable in response to a least significant bit (D0) of the 3-bit digital signal (D2, D1, D0) to open or close. Each of the second switches (G8˜G11) is connected to a corresponding adjacent pair of the first switches (G0˜G7), and is operable in response to a middle bit (D1) of the 3-bit digital signal (D2, D1, D0) to open or close. Each of the third switches (G12˜Gl3) is connected to a corresponding adjacent pair of the second switches (G8˜G11), and is operable in response to a most significant bit (D2) of the 3-bit digital signal (D2, D1, D0) to open or close. For example, if the 3-bit digital signal (D2, D1, D0) inputted into the switch multiplexer 21 is “101”, then the switches (G5), (G10), (G13) are closed such that the voltage
  (            -              V        ref              +                  5        8            ⁢      ΔV        )at the intermediate node (n5) is tapped to the output node Vout.
Although decoding of this conventional D/A converter 2 is simpler than that of the previous conventional D/A converter 1, the number of resistors and switches required for its operation is still large.